Archive-name: ai-faq/neural-nets/part7 Last-modified: 1995/07/06 URL: http://wwwipd.ira.uka.de/~prechelt/FAQ/neural-net-faq.html Maintainer: prechelt@ira.uka.de (Lutz Prechelt)
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The Number 1 of each volume of the journal "Neural Networks" has a list of some dozens of suppliers of Neural Network support: Software, Hardware, Support, Programming, Design and Service.
There is an article by J.A. Hegt (Eindhoven) from 1993 available from ftp://ftp.urc.tue.nl/pub/neural/hardware_general.ps.gz
Another overview article from 1995 can be found in ftp://ftp.mrc-apu.cam.ac.uk/pub/nn/murre/neurhard.ps
Here is a short list of companies:
HNC Inc. 5930 Cornerstone Court West San Diego, CA 92121-3728 619-546-8877 Phone 619-452-6524 Fax HNC markets: Database Mining Workstation (DMW), a PC based system that builds models of relationships and patterns in data. AND The SIMD Numerical Array Processor (SNAP). It is an attached parallel array processor in a VME chassis with between 16 and 64 parallel floating point processors. It provides between 640 MFLOPS and 2.56 GFLOPS for neural network and signal processing applications. A Sun SPARCstation serves as the host. The SNAP won the IEEE 1993 Gordon Bell Prize for best price/performance for supercomputer class systems.
10260 Campus Point Drive MS 71, San Diego CA 92121 (619) 546 6148 Fax: (619) 546 6736
30 Skyline Drive Lake Mary FL 32746-6201 (407) 333-4379 MicroDevices makes MD1220 - 'Neural Bit Slice' Each of the products mentioned sofar have very different usages. Although this sounds similar to Intel's product, the architectures are not.
2250 Mission College Blvd
Santa Clara, Ca 95052-8125
Attn ETANN, Mail Stop SC9-40
(408) 765-9235
Intel was making an experimental chip (which is no longer produced):
80170NW - Electrically trainable Analog Neural Network (ETANN)
It has 64 'neurons' on it - almost fully internally connectted
and the chip can be put in an hierarchial architecture to do 2 Billion
interconnects per second.
Support software by
California Scientific Software
10141 Evening Star Dr #6
Grass Valley, CA 95945-9051
(916) 477-7481
Their product is called 'BrainMaker'.
Penn Center West Bldg IV Suite 227 Pittsburgh PA 15276 They only sell software/simulator but for many platforms.
7a Lavant Street Peterfield Hampshire GU32 2EL United Kingdom Tel: +44 730 60256
1400 NW Compton Drive Suite 340 Beaverton, OR 97006 U. S. A. Tel: 503-690-1236; FAX: 503-690-1249
4730 Walnut St., Suite 101B Boulder, CO 80301 Voice: (303) 442-3539 Fax: (303) 442-2854 Internet: techsupport@ndx.com NDX sells a number neural network hardware products: NDX Neural Accelerators: a line of i860-based accelerator cards for the PC that give up to 45 million connections per second for use with the DynaMind neural network software. iNNTS: Intel's 80170NX (ETANN) Neural Network Training System. NDX's president was one of the co-designers of this chip.
NEURO-COMPUTING IC's: * DANN050L (dendro-dendritic artificial neural network) + 50 neurons fully connected at the input + on-chip digital learning capability + 6 billion connections/sec peak speed + learns 7 x 7 template in < 50 nsec., recalls in < 400 nsec. + low power < 100 milli Watts + 64-pin package * NCA717D (neuro correlator array) + analog template matching in < 500 nsec. + analog input / digital output pins for real-time computation + vision applications in stereo and motion computation + 40-pin package NEURO COMPUTING BOARD: * ICT1050 + IBM PC compatible or higher + with on-board DANN050L + digital interface + custom configurations available Contact: IC Tech (Innovative Computing Technologies, Inc.) 4138 Luff Court Okemos, MI 48864 (517) 349-4544 ictech@mcimail.com
\subsection*{Digital}
\subsubsection{Special Computers}
{\bf AAP-2}
Takumi Watanabe, Yoshi Sugiyama, Toshio Kondo, and Yoshihiro Kitamura.
Neural network simulation on a massively parallel cellular array
processor: AAP-2.
In International Joint Conference on Neural Networks, 1989.
{\bf ANNA}
B.E.Boser, E.Sackinger, J.Bromley, Y.leChun, and L.D.Jackel.\\
Hardware Requirements for Neural Network Pattern Classifiers.\\
In {\it IEEE Micro}, 12(1), pages 32-40, February 1992.
{\bf Analog Neural Computer}
Paul Mueller et al.
Design and performance of a prototype analog neural computer.
In Neurocomputing, 4(6):311-323, 1992.
{\bf APx -- Array Processor Accelerator}\\
F.Pazienti.\\
Neural networks simulation with array processors.
In {\it Advanced Computer Technology, Reliable Systems and Applications;
Proceedings of the 5th Annual Computer Conference}, pages 547-551.
IEEE Comput. Soc. Press, May 1991. ISBN: 0-8186-2141-9.
{\bf ASP -- Associative String Processor}\\
A.Krikelis.\\
A novel massively associative processing architecture for the
implementation artificial neural networks.\\
In {\it 1991 International Conference on Acoustics, Speech and
Signal Processing}, volume 2, pages 1057-1060. IEEE Comput. Soc. Press,
May 1991.
{\bf BSP400}
Jan N.H. Heemskerk, Jacob M.J. Murre, Jaap Hoekstra, Leon H.J.G.
Kemna, and Patrick T.W. Hudson.
The bsp400: A modular neurocomputer assembled from 400 low-cost
microprocessors.
In International Conference on Artificial Neural Networks. Elsevier
Science, 1991.
{\bf BLAST}\\
J.G.Elias, M.D.Fisher, and C.M.Monemi.\\
A multiprocessor machine for large-scale neural network simulation.
In {\it IJCNN91-Seattle: International Joint Conference on Neural
Networks}, volume 1, pages 469-474. IEEE Comput. Soc. Press, July 1991.
ISBN: 0-7883-0164-1.
{\bf CNAPS Neurocomputer}\\
H.McCartor\\
Back Propagation Implementation on the Adaptive Solutions CNAPS
Neurocomputer.\\
In {\it Advances in Neural Information Processing Systems}, 3, 1991.
{\bf GENES~IV and MANTRA~I}\\
Paolo Ienne and Marc A. Viredaz\\
{GENES~IV}: A Bit-Serial Processing Element for a Multi-Model
Neural-Network Accelerator\\
Proceedings of the International Conference on Application Specific Array
Processors, Venezia, 1993.
{\bf MA16 -- Neural Signal Processor}
U.Ramacher, J.Beichter, and N.Bruls.\\
Architecture of a general-purpose neural signal processor.\\
In {\it IJCNN91-Seattle: International Joint Conference on Neural
Networks}, volume 1, pages 443-446. IEEE Comput. Soc. Press, July 1991.
ISBN: 0-7083-0164-1.
{\bf MANTRA I}\\
Marc A. Viredaz\\
{MANTRA~I}: An {SIMD} Processor Array for Neural Computation
Proceedings of the Euro-ARCH'93 Conference, {M\"unchen}, 1993.
{\bf Mindshape}
Jan N.H. Heemskerk, Jacob M.J. Murre Arend Melissant, Mirko Pelgrom,
and Patrick T.W. Hudson.
Mindshape: a neurocomputer concept based on a fractal architecture.
In International Conference on Artificial Neural Networks. Elsevier
Science, 1992.
{\bf mod 2}
Michael L. Mumford, David K. Andes, and Lynn R. Kern.
The mod 2 neurocomputer system design.
In IEEE Transactions on Neural Networks, 3(3):423-433, 1992.
{\bf NERV}\\
R.Hauser, H.Horner, R. Maenner, and M.Makhaniok.\\
Architectural Considerations for NERV - a General Purpose Neural
Network Simulation System.\\
In {\it Workshop on Parallel Processing: Logic, Organization and
Technology -- WOPPLOT 89}, pages 183-195. Springer Verlag, Mars 1989.
ISBN: 3-5405-5027-5.
{\bf NP -- Neural Processor}\\
D.A.Orrey, D.J.Myers, and J.M.Vincent.\\
A high performance digital processor for implementing large artificial
neural networks.\\
In {\it Proceedings of of the IEEE 1991 Custom Integrated Circuits
Conference}, pages 16.3/1-4. IEEE Comput. Soc. Press, May 1991.
ISBN: 0-7883-0015-7.
{\bf RAP -- Ring Array Processor }\\
N.Morgan, J.Beck, P.Kohn, J.Bilmes, E.Allman, and J.Beer.\\
The ring array processor: A multiprocessing peripheral for connectionist
applications. \\
In {\it Journal of Parallel and Distributed Computing}, pages
248-259, April 1992.
{\bf RENNS -- REconfigurable Neural Networks Server}\\
O.Landsverk, J.Greipsland, J.A.Mathisen, J.G.Solheim, and L.Utne.\\
RENNS - a Reconfigurable Computer System for Simulating Artificial
Neural Network Algorithms.\\
In {\it Parallel and Distributed Computing Systems, Proceedings of the
ISMM 5th International Conference}, pages 251-256. The International
Society for Mini and Microcomputers - ISMM, October 1992.
ISBN: 1-8808-4302-1.
{\bf SMART -- Sparse Matrix Adaptive and Recursive Transforms}\\
P.Bessiere, A.Chams, A.Guerin, J.Herault, C.Jutten, and J.C.Lawson.\\
From Hardware to Software: Designing a ``Neurostation''.\\
In {\it VLSI design of Neural Networks}, pages 311-335, June 1990.
{\bf SNAP -- Scalable Neurocomputer Array Processor}
E.Wojciechowski.\\
SNAP: A parallel processor for implementing real time neural networks.\\
In {\it Proceedings of the IEEE 1991 National Aerospace and Electronics
Conference; NAECON-91}, volume 2, pages 736-742. IEEE Comput.Soc.Press,
May 1991.
{\bf Toroidal Neural Network Processor}\\
S.Jones, K.Sammut, C.Nielsen, and J.Staunstrup.\\
Toroidal Neural Network: Architecture and Processor Granularity
Issues.\\
In {\it VLSI design of Neural Networks}, pages 229-254, June 1990.
{\bf SMART and SuperNode}
P. Bessi`ere, A. Chams, and P. Chol.
MENTAL : A virtual machine approach to artificial neural networks
programming. In NERVES, ESPRIT B.R.A. project no 3049, 1991.
\subsubsection{Standard Computers}
{\bf EMMA-2}\\
R.Battiti, L.M.Briano, R.Cecinati, A.M.Colla, and P.Guido.\\
An application oriented development environment for Neural Net models on
multiprocessor Emma-2.\\
In {\it Silicon Architectures for Neural Nets; Proceedings for the IFIP
WG.10.5 Workshop}, pages 31-43. North Holland, November 1991.
ISBN: 0-4448-9113-7.
{\bf iPSC/860 Hypercube}\\
D.Jackson, and D.Hammerstrom\\
Distributing Back Propagation Networks Over the Intel iPSC/860
Hypercube}\\
In {\it IJCNN91-Seattle: International Joint Conference on Neural
Networks}, volume 1, pages 569-574. IEEE Comput. Soc. Press, July 1991.
ISBN: 0-7083-0164-1.
{\bf SCAP -- Systolic/Cellular Array Processor}\\
Wei-Ling L., V.K.Prasanna, and K.W.Przytula.\\
Algorithmic Mapping of Neural Network Models onto Parallel SIMD
Machines.\\
In {\it IEEE Transactions on Computers}, 40(12), pages 1390-1401,
December 1991. ISSN: 0018-9340.
------------------------------------------------------------------------That's all folks (End of the Neural Network FAQ).
Acknowledgements: Thanks to all the people who helped to get the stuff
above into the posting. I cannot name them all, because
I would make far too many errors then. :->
No? Not good? You want individual credit?
OK, OK. I'll try to name them all. But: no guarantee....
THANKS FOR HELP TO:
(in alphabetical order of email adresses, I hope)
Bye LutzPrevious part is part 6.
Neural network FAQ / Lutz Prechelt, prechelt@ira.uka.de